BICs (Bridge IC) are standalone devices deployed within a Data Center that enable monitoring a multi-host system using a single BMC device.
by facebookC
Last 12 weeks · 52 commits
4 of 6 standards met
[Task Description] YV4T1M-2231 Add an OEM IPMI command (0x30 0x49) to allow the BIOS to dynamically control the postcode filter status. Ensure the system can distinguish whether the setting is driven by the BIOS Setup Knob or an OS/BMC override. [Motivation] Add the capability to configure the Post-code filter within the BIOS menu to provide engineers with more intuitive and real-time debugging control. [Design] State Synchronization Logic: Introduce a 'Valid' bit where 0 represents the BIOS Knob setting and 1 represents an OS/BMC override. When the filter is controlled via BMC/PLDM (pldmtool) or legacy ipmitool commands, the system will automatically synchronize and update the 'Valid' bit to 1 to ensure consistency of the status source. [Test log] [Host console] Check status [root@QE-SSD-OS-YV4 ~]# ipmitool raw 0x30 0x49 01 01 Disable the filter [root@QE-SSD-OS-YV4 ~]# ipmitool raw 0x30 0x49 0x00 00 01 Check status [root@QE-SSD-OS-YV4 ~]# ipmitool raw 0x30 0x49 00 01 Enable the filter [root@QE-SSD-OS-YV4 ~]# ipmitool raw 0x30 0x49 0x01 01 01 [root@QE-SSD-OS-YV4 ~]# ipmitool raw 0x30 0x49 01 01 [root@QE-SSD-OS-YV4 ~]# [BIC console] uart:~$ [00:01:16.920,000] plat_pcc: Postcode filter disabled [00:01:22.126,000] plat_pcc: Postcode filter enabled [00:03:01.625,000] plat_pcc: Postcode filter disabled
Repository: facebook/OpenBIC. Description: BICs (Bridge IC) are standalone devices deployed within a Data Center that enable monitoring a multi-host system using a single BMC device. Stars: 64, Forks: 55. Primary language: C. Languages: C (98.9%), Python (0.7%), CMake (0.4%), Shell (0%). License: Apache-2.0. Latest release: oby35-hd-2022.37.01 (3y ago). Open PRs: 3, open issues: 5. Last activity: 19h ago. Community health: 75%. Top contributors: SaraSYLin, LoraLin1, MouchenHung-QUANTA, Yi-Shum, GoldenBug, Victor-Jhong, MarshallZhan-wiwynn, LisaChang-Quanta, HungYi-Li, Quanta-YangChen and others.
Modify CPU thermal sensor configurations to correct thermal margin representation and threshold settings. (GC20T5T7-134) [Motivation] Fix CPU thermal margin sign representation Correct threshold settings for CPU thermal sensors [Design] 1. CPU Thermal Margin Sign Correction: Remove negative conversion in post_cpu_margin_read() Current implementation: Use raw value directly from sensor 2. Sensor Unit Configuration Update: Change sensor unit from 0x00 to 0x80 (enable 2's complement) Applies to: MB_SOC_THERMAL_MARGIN_C (0x14) Purpose: Support negative temperature values in MB_SOC_THERMAL_MARGIN_C reading 3. Threshold Configuration Adjustment: MB_SOC_THERMAL_MARGIN_C (0x14): UNR : 125 → 0 MB_SOC_TJMAX_C (0x15): UNR : 125 → 0 [Test Result] Verified CPU thermal sensor readings and thresholds on GC2-ES platform: root@bmc-oob:~# sensor-util server --thr | grep -iE "SOC_(.?)_C" MB_SOC_CPU_TEMP_C (0x5) : 35.000 C LNR: NA MB_SOC_THERMAL_MARGIN_C (0x14) : -43.000 C LNR: NA MB_SOC_TJMAX_C (0x15) : 78.000 C LNR: NA All CPU thermal sensors report correctly with proper values and thresholds.
Add missing copyright headers for the following files 1. meta-facebook/sb-rb/src/platform/plat_ioexp.c 2. meta-facebook/sb-rb/src/shell/shell_clock_ctrl.c 3. meta-facebook/sb-rb/src/shell/shell_iris_power.c 4. meta-facebook/sb-rb/src/shell/shell_jtag_mux.c 5. meta-facebook/sb-rb/src/shell/shell_vr_hot_switch.c